The following ghost cancelling system has been proposed in the prior art. As, for example, shown in FIG. 1, a signal received by an antenna 1 is supplied through a tuner 2 and a video intermediate frequency amplifier 3 to a video detector circuit 4 which then detects a video signal. This video signal is supplied through a delay circuit 5 with a delay time corresponding to the eliminating period of a pre-ghost to a composer 6 and a ghost cancelling signal imitating the ghost derived from a transversal filter that will be described later is supplied to the composer 6 so that the video signal with the ghost cancelled out is delivered from the composer 6 to an output terminal 7.
The video signal derived from the video detector circuit 4 is supplied to a delay circuit 8 that forms a part of the transversal filter. In this delay circuit 8, delay elements, each of which takes a sampling period (for example, 10 [ns] (nano seconds)) as a unit of delay, are connected in a plurality of stages (n number) to establish a delay time equal to the eliminating period of the pre-ghost and, n taps are led out from the respective stages. The signals from these n taps are respectively supplied to weighting circuits 9.sub.1, 9.sub.2, . . . 9.sub.n each of which is formed of a multiplier.
The signal from the end of the delay circuit 8 is supplied to a terminal 10f of a mode switch 10 and the output signal from the composer 6 is supplied to the other terminal 10b of the mode switch 10. The signal derived from this mode switch 10 is supplied to a delay circuit 11. This delay circuit 11 is formed of delay elements, each delay element taking a sampling period as a unit delay time, connected in a plurality of stages (m number) to have a delay time equal to an eliminating period of a delay-ghost and m taps are led out from the respective stages thereof. The signals from these taps are respectively supplied to weighting circuits 12.sub.1, 12.sub.2, . . . 12.sub.n, each of which is formed of a multiplier.
The video signal from the composer 6 is supplied to a subtracting circuit 13. Further, the video signal from the delay circuit 5 is supplied to a synchronizing separator circuit 14 and the separated synchronizing signal therefrom is fed to a standard wave forming circuit 15 and a low-pass filter 16 by which a standard waveform approximate to a step-waveform of a rising edge VE of the vertical synchronizing signal is formed. This standard waveform is supplied to the subtracting circuit 13.
The signal from this subtracting circuit 13 is supplied to a differentiation circuit 17 which then detects the ghost.
For the ghost detecting signal, there is employed such a signal that is contained in a standard television signal and which is not affected by other signals during the period as long as possible, for example, the vertical synchronizing signal. That is, as shown in FIG. 2, the periods .+-.1/2 H (H is the horizontal period) before and after the rising edge VE of the vertical synchronizing signal are not affected by other signals. Therefore, the afore-noted standard waveform is subtracted from the signal in this period and the subtracted signal is differentiated to thereby detect a weighting factor.
When there is contained a ghost with a phase difference of 45.degree. from a desired signal and with a delay time .tau.(=.omega..sub.c .tau. where .omega..sub.c is the video carrier angular frequency in the high frequency stage), the video signal with the waveform as shown in FIG. 3A appears. While, if this signal is differentiated and inverted in polarity, a ghost detecting signal with a differentiation waveform as shown in FIG. 3B is provided. This differentiation waveform can approximately be regarded as an impulse response to the ghost.
The ghost detecting signal of the differentiation waveform appearing from the differentiation circuit 17 is supplied through an amplifier 18 to demultiplexers 19 and 20 which are connected in series. The demultiplexers 19 and 20 each have such a construction similar to the delay circuits 8 and 11 in which delay elements, each of which takes a sampling period as a unit of delay time, are connected in a plurality of stages and m and n taps are led out from the respective stages thereof. The outputs of the respective taps are respectively supplied to switching circuits 21.sub.1, 21.sub.2, . . . 21.sub.n and 22.sub.1, 22.sub.2, . . . 22.sub.m.
The vertical synchronizing signal from the synchronizing separator circuit 14 is fed to a gate pulse generator 23 which then generates a gate pulse having a pulse width corresponding to an interval from the rising edge VE of the synchronizing signal to the last end of the 1/2 H period. On the basis of this gate pulse, the switching circuits 21.sub.1 to 22.sub.m are turned on, respectively.
The signals from the switching circuits 21.sub.1 to 22.sub.m are respectively supplied to analog accumulative adders 24.sub.1, 24.sub.2 . . . 24.sub.n and 25.sub.1, 25.sub.2, . . . 25.sub.m. The signals from these analog accumulative adders 24.sub.1 to 25.sub.m are respectively supplied to the weighting circuits 9.sub.1 to 9.sub.n and 12.sub.1 to 12.sub.m.
The outputs of these weighting circuits 9.sub.1 to 9.sub.n and 12.sub.1 to 12.sub.m are added together in an adding circuit 26 to form a ghost cancelling signal. This ghost cancelling signal is supplied to the composer 6.
As described above, the delay circuits 8 and 11, the weighting circuits 9.sub.1 to 9.sub.n and 12.sub.1 to 12.sub.m and the adding circuit 26 constitute the transversal filter and thereby the ghost is cancelled out. In this case, even after the deformation of the waveform in the periods from the rising edge of a certain vertical synchronizing signal and the .+-.1/2 H before and after the foregoing rising edge is detected and then a weighting factor is decided, if there still remains a ghost which is not cancelled out, in order to carry out the above detection and to reduce the remaining ghost, there are provided the analog accumulative adders 24.sub.1 to 25.sub.m, respectively.
The changing of the mode switch 10 enables the delay-ghost cancelling to be selectively changed from the feedforward mode to the feedback mode and vice versa.
FIG. 4 shows a case in which an input-adding type transversal filter is employed to cancel out a ghost. In the figure, like parts corresponding to those in FIG. 1 are marked with the same references and will not be described in detail.
In the figure, the video signal derived from the video detector circuit 4 is supplied to the weighting circuits 9.sub.1 to 9.sub.n and the signals from the weighting circuits 9.sub.1 to 9.sub.n are respectively supplied to input terminals of a delay circuit 8'. This delay circuit 8' consists of delay elements, each of which takes a sampling period as a unit, connected in n stages and n input terminals provided at respective stages between adjacent ones.
The signals at the input and output sides of the composer 6 are supplied to terminals 10f' and 10b' of a mode switch 10'. The signal from this mode switch 10' is supplied to the weighting circuits 12.sub.1 to 12.sub.m and the signals from these weighting circuits 12.sub.1 to 12.sub.m are respectively supplied to input terminals of a delay circuit 11'. This delay circuit 11' consists of delay elements, each delay element having a sampling period as a unit, connected in m stages and m input terminals provided at respective stages between adjacent ones.
The signals respectively derived from the ends of these delay circuits 8' and 11' are added together in an adding circuit 26' to form a ghost cancelling signal. This ghost cancelling signal is supplied to the composer 6.
With this circuit arrangement, similarly to the ghost cancelling circuit that employs the afore-noted output adding type transversal filter, the ghost can be cancelled out, too.
Further, in the above circuit, it may be possible that without providing the differentiation circuit 17, the difference between the outputs of the adjacent bits of the demultiplexers 19 and 20 is used to produce a differential output and the weighting can be carried out by using this differential output.
Furthermore, it may be possible that the demultiplexers 19 and 20 and the delay circuits 8 and 11 are made common, upon weighting, the weighting signal is supplied to the delay circuit, stored in a memory circuit, and thereafter the weighting is carried out by the stored signal.
As described above, it is possible to cancell out the ghost in the video signal stage.
In the above ghost cancelling system, the generation of the standard waveform and the switching timing of the switching circuits 21.sub.1 to 22.sub.m take the rising edge of, for example, the vertical synchronizing signal as a reference time point. In this case, it is requested that the reference time point is detected with very high precision and it is experimentally confirmed that the accuracy within 35n sec is required.
However, since the prior art synchronizing separator circuit includes a low-pass filter in its circuitry, information of high frequency band is dropped out and the rising edge of the signal or the like is blunted. Therefore, there is then a fear that if the reference time point is detected from the vertical synchronizing signal thus separated, a time delay will occur.
On the other hand, it is proposed that a masking pulse of about 1/2 H period including the rising edge of, for example, the vertical synchronizing signal is formed and the transit of the rising edge is directly detected by using this masking pulse and the video signal.
In this method, however, if the masking pulse is formed at incorrect position due to the influence of noise and so on, there may be such a fear that a different transit is detected with the result that the reference time point becomes incorrect much. This is a serious problem particularly because the ghost cancelling system is frequently used in the poor S/N (signal-to-noise) ratio such as a weak electric field and the like.
By the way, since the width of the masking pulse may be 1/2 H period including the rising edge of the vertical synchronizing signal, it is not requested that this masking pulse is formed with so high accuracy. Further, since the prior art synchronizing separator circuit with a low-pass filter includes the low-pass filter, noise is suppressed and this synchronizing separator circuit is less in mis-operation.
Therefore, the present inventor has previously proposed the following circuit. In FIG. 5, reference numeral 31 designates an input terminal to which a video signal is supplied. The signal from this terminal 31 is supplied to a synchronizing separator circuit that consists of a comparator 32 and a low-pass filter 33, and the signal (FIG. 6A) from the low-pass filter 33 is supplied to a synchronizing separator circuit 34 consisting of a low-pass filter. The vertical synchronizing signal (FIG. 6B) separated by this separator circuit 34 is supplied to a masking pulse generating circuit 35 which then generates, for example, a triangular wave (FIG. 6C). And, on the basis of this triangular wave and the reference potential (shown by a broken line), there is formed a masking pulse (FIG. 6D) that corresponds to 1/2 H period including the rising edge of the vertical synchronizing signal. This masking pulse is supplied to the control terminal of a comparator 36. Further, the signal applied to the terminal 31 is supplied through an amplifier 37 to the comparator 36. When the falling edge of the signal, for example, is detected by the comparator 36, the rising edge (FIG. 6E) of the vertical synchronizing signal, which will become the reference time point, is detected and then developed at an output terminal 38 is a t=0 pulse (FIG. 6F) that results from inverting the above rising edge of the vertical synchronizing signal.
Alternatively, in FIG. 7, the signal from the input terminal 31 is supplied through a clamping capacitor 41 to the connection point between a resistor 43 and a constant current source 44 in a series circuit formed of a transistor 42, the resistor 43 and the constant current source 44 which forms a bias circuit. The signal at the connection point is supplied to a base of one transistor 45 which forms a differential amplifier, while a base of the other transistor 46 is supplied with a voltage from the connection point between a resistor 48 and a constant current source 49 in a series circuit formed of a transistor 47, the resistor 48 and the constant current source 49 that forms a bias circuit. Then, the signal current flowing through the collector of the transistor 45 is derived through a current mirror circuit 50.
Further, this signal is supplied through a switch 51 to a low-pass filter 52 and a buffer amplifier 53 and also supplied through a switch 54 to a low-pass filter 55 and a buffer amplifier 56. The signals from these buffer amplifiers 53 and 56 are added together by resistors 57 and 58 and then fed to a comparator 59. Also, the signal from the current mirror circuit 50 is supplied to the comparator 59.
The signal from this comparator 59 is supplied to a clock terminal of a D-type flip-flop circuit 60. The masking pulse from the generator circuit 35 is supplied to the D terminal of the flip-flop circuit 60 and at the same time the polarity thereof is inverted and then supplied to the clear terminal of the flip-flop circuit 60, whereby the output of the flip-flop circuit 60 is developed at the output terminal 38.
In this circuitry, from the current mirror circuit 50 derived is a signal as, for example, shown in FIG. 8A. For this signal, the switches 51 and 54 are respectively turned on during the periods as, for example, shown in FIGS. 8B and 8C. Accordingly, the buffer amplifiers 53 and 56 respectively produce potentials (E.sub.l and E.sub.2) which are respectively correspond to the pedestal and the sync tip level of the synchronizing signal. These potentials are added together by the resistors 57 and 58. If the resistance values of the resistors 57 and 58 are respectively taken as R.sub.l and R.sub.2, a potential E.sub.3 that results from the addition becomes as ##EQU1## If the condition R.sub.2 &lt;R.sub.1 is satisfied, the above potential E.sub.3 becomes as ##EQU2## When this potential E.sub.3 is supplied to the comparator 59, the comparator 59 produces a signal as shown in FIG. 8D. While, the masking pulse generating circuit 35 produces a signal as shown in FIG. 8E. When these signals are supplied to the flip-flop circuit 60, a signal as shown in FIG. 8F is developed at the output terminal 38.
As described above, the reference time point is detected.
However, in these apparatus, the gate pulse that makes the switches 21.sub.1 to 21.sub.n and 22.sub.1 to 22.sub.m on is formed by using a time point which is delayed by a delay time corresponding to the delay time of the demultiplexer 19 for the delay-ghost is calculated from the time point of the rising edge of, for example, the vertical synchronizing signal by a monostable multivibrator and the like. Accordingly, when the delay characteristics of the monostable multivibrator and the demultiplexer are changed due to the change of temperature and so on, the time point at which the switch is turned on is displaced and hence there is a fear that the correct memory is no longer carried out.
Therefore, in order to remove the above shortcoming, the following method is considered.
In FIG. 9, the signal from the synchronizing separator circuit 14 is supplied to a pilot signal generating circuit 61 which then produces a pilot signal as shown in FIG. 10B at the time point corresponding to the rising edge of the vertical synchronizing signal as shown in FIG. 10A. This signal is supplied to an adder 62 that is provided between the amplifier 18 and the demultiplexer 19, in which it is superimposed on the ghost detection signal. Accordingly, after the detection period T0 shown in FIG. 10C elapses, the above pilot signal is produced at the last tap of the demultiplexer 19. The signal on the last tap is supplied to a pilot pulse detecting circuit 63 and the detected signal therefrom is supplied to a waveform shaping circuit 64 which then produces a gate pulse signal.
Since at this time point the ghost detection signals in the ghost detection interval are respectively distributed on the respective taps of the demultiplexers 19 and 20 and the gate pulse signal is produced at this time point, the signals on the respective taps are stored in the analog accumulative adders 24.sub.1 to 24.sub.n and 25.sub.1 to 25.sub.m.
As described above, the ghost detecting signals are stored in the weighting storing analog accumulative adders 24.sub.1 to 24.sub.n and 25.sub.1 to 25.sub.m.
However, in the case of this apparatus, since the detection of the pilot pulse is carried out at the intermediate stage between the demultiplexers 19 and 20, the inserted pilot signal affects at least one of the outputs from the demultiplexers 19 and 20 so that the correct weighting becomes impossible.